1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Background Art
In general, a DRAM (dynamic random access memory) is known as an exemplary semiconductor device, as disclosed in Japanese Patent Laying-Open No. 8-339681 (1996), for example.
The DRAM disclosed in the aforementioned Japanese Patent Laying-Open No. 8-339681 equalizes the difference between a potential corresponding to data “1” read from a capacitor of a memory cell on a bit line and a reference potential with the difference between a potential corresponding to data “0” and the reference potential by increasing both of the potentials corresponding to the data “1” and “0” respectively in data reading, in order to compensate reduction of the difference between the potential corresponding to the data “1” and the reference potential beyond the difference between the potential corresponding to the data “0” and the reference potential. Thus, the DRAM disclosed in the aforementioned Japanese Patent Laying-Open No. 8-339681 equalizes the difference between an input potential corresponding to the data “1” introduced into a sense amplifier through the bit line and the reference potential with the difference between an input potential corresponding to the data “0” introduced into the sense amplifier through another bit line and the reference potential when determining the data read from the memory cell onto the bit line through the sense amplifier.
In the DRAM disclosed in the aforementioned Japanese Patent Laying-Open No. 8-339681, however, the difference between the potentials of the bit lines corresponding to the data “1” and “0” respectively after the potential increase remains identical to that before the potential increase. In other words, the difference between the potentials of the bit lines corresponding to the data “1” and “0” respectively is not increased after the potential increase. Therefore, it may disadvantageously be difficult to determine whether the input potential is higher or lower than the reference potential if the difference between the potentials (input potentials) of the bit lines corresponding to the data “0” and “1” respectively and the reference potential is reduced due to reduction of the quantity of charges corresponding to the data held in the capacitors of the memory cells following refinement of the capacitors. Thus, the accuracy for determining whether the input potentials are higher or lower than the reference potential is disadvantageously reduced.